This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-143588, filed May 14, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device having a test mode. More specifically, the present invention relates to a semiconductor memory device which allows its memory chip to perform, even after being packaged, a particular operation (for example, testing of the memory cell array) that is not part of its normal operations.
2. Description of the Related Art
Conventionally, semiconductor memory devices are supplied with signals at test pads formed on their respective memory chips at wafer test time. By this means, various tests are run. For example, the memory cell array is subjected to a given operation that is not part of normal memory operations. Such tests can be carried out in a short time. However, such tests cannot be made on packaged final products. For this reason, the demand has increased for developing semiconductor memory devices on which tests can be carried out even after packaging.
To meet such a demand, a semiconductor memory device has recently been developed which is configured to automatically enter a test mode when a high voltage is applied to an input pin. The semiconductor memory device has a high-voltage detection circuit connected to its input pin to detect the application of a voltage higher than the normal operating voltage (Vcc). For example, with Vcc=3.3 V, a test is carried out when a voltage of not less than 6.5 V is applied to the input pin. With such a semiconductor memory device, packaged final products can be tested without using a special input pin. Accordingly, this kind of semiconductor memory device has come into widespread use.
However, the semiconductor memory device as described above has the following problems associated with it:
The switching voltage of the high-voltage detection circuit is subject to variation due to variations in process parameters such as the threshold voltage, Vth. Therefore, in the worst case there arises the possibility that a test may be carried out in error due to noise input during the normal memory operation.
As memory cells are made smaller as a result of advances in fine pattern technology, the gate insulating film of the transistors of each of memory cell becomes thinner. Therefore, the adverse effect on reliability of applying a high voltage to the input pin has become a problem. It is expected that the gate insulating film will become increasingly thinner in future. Thus, the conventional method of applying a high voltage to the input pin is not desirable from the viewpoint of reliability.
As described above, a semiconductor memory device has conventionally been developed which can be tested even after being packaged by applying a high voltage to the input pin. However, there arises the possibility of malfunction due to noise and reliability becomes a problem as the thickness of the gate insulating film is reduced.
According to an aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array from or to which data is read or written; an identification circuit to identify a particular signal which allows a particular operation that is not part of normal operations to read or write data from or to the memory cell array to be performed on the memory cell array; and a control circuit which performs the particular operation on the memory cell array when the particular signal is identified by the identification circuit.